High data reliability, high speed of memory access, reduced chip size and low power consumption are features that are demanded from semiconductor memory. In recent years, there has been an effort to further reduce power consumption.
In a semiconductor memory device, such as dynamic random access memory (DRAM), memory cells are refreshed in order to preserve the stored data. The semiconductor memory device typically has a normal operation mode and a self-refresh operation mode. The semiconductor memory device may conduct a refresh operation under the three conditions. First, the semiconductor memory device may conduct the refresh operation responsive to each auto-refresh (AREF) command. Second, the semiconductor memory device may conduct the refresh operation once at a self-refresh operation mode entry. Third, the semiconductor memory device may conduct the refresh operation responsive to refresh pulses provided by a signal generator, such as an oscillator.
In the normal operation mode, the semiconductor memory device is active. A clock enable signal CKE controls whether the semiconductor memory device is active (e.g., CKE having a logic high level). In the self-refresh operation mode, typically the semiconductor memory device is in a stand-by state. The clock enable signal CKE controls whether the semiconductor memory device is inactive (e.g., CKE having a logic low level). In order to reduce power consumption, an interval of executing the refresh operation in the self-refresh operation mode is longer than in the normal operation mode activated by the auto-refresh (AREF) command.
FIG. 1A is a timing diagram of signals in a normal operation mode and in a self-refresh operation mode in a semiconductor memory device. For example, auto refresh commands (AREF) are issued from a controller. Refresh operations are performed in accordance with the auto refresh commands when in the normal operation mode (e.g., while the clock enable signal CKE is at the logic high level). Intervals of the auto refresh commands are controlled by the controller. On the other hand, in the self-refresh operation mode (e.g., while the clock enable signal CKE is at the logic low level) the refresh operations are performed in accordance with a signal OSC, which is from a signal generation circuit, such as an oscillator, in the semiconductor memory device.
When the clock enable signal CKE becomes inactive (e.g., transition to the logic low level), the semiconductor memory device activates the oscillator to generate an internal refresh signal responsive to the signal OSC in the self-refresh operation mode, and refresh operations are performed in synchronism with the internal refresh signal. Intervals of the internal refresh signal are determined based on data retention ability of semiconductor memory device. Thus, the intervals of the internal refresh signal may be different, possibly longer than the intervals of the auto refresh commands (AREF). Refresh operation intervals of the auto-refresh command AREF in the normal operation mode tend to be shorter than necessary, resulting in more frequent refresh operation, and may cause higher power consumption. As described the above, the semiconductor memory device may be able to store data for a time longer than the interval of the auto-refresh command AREF, such as for the intervals of the signal OSC.
A refresh operation may be executed each time the semiconductor memory device enters a self-refresh operation mode. When the semiconductor memory device frequently switches between the normal operation mode and the self-refresh operation mode, the refresh operations from entering the self-refresh operation mode may also occur frequently. FIG. 1B is a timing diagram of signals in a normal operation mode and in a self-refresh operation mode in a semiconductor memory device. In this example, the semiconductor memory device switches between the normal operation mode and the self-refresh operation mode frequently, and as shown a refresh operation is performed each time the self-refresh operation mode is entered. If the period of the self-refresh operation mode is much shorter (e.g., a quarter of the interval of the signal OSC) than the time to provide the active signal of OSC, and if the active period of the normal operation is much shorter (e.g., a quarter of the interval of the signal OSC) than the time to receive the auto-refresh command AREF, refresh operations may be performed at each entry of the self-refresh operation mode, which may be twice as frequent as the interval of the active OSC.
Thus, the refresh operation intervals of each entry to the self-refresh operation mode tend to be more frequent than necessary and may cause unnecessary power consumption. For example, semiconductor memory devices used for mobile devices, such as Mobile DRAMs, are configured to quickly transit to the self-refresh operation mode when the semiconductor memory device does not receive read/write commands from the controller, and may experience the failure of the data retention or excess power consumption as described above due to frequent entries into the self-refresh operation mode.